1. Field of the Invention
This invention relates to a semiconductor device and a process for producing the same. More particularly, it relates to a method for interconnecting wirings of a semiconductor integrated circuit.
2. Related Background Art
In recent years, the degree of integration of semiconductor devices has been made higher year after year with a miniaturization of the devices. Since, however, the number of wirings required increases with an increase in the degree of integration, it is not too much to say under existing circumstances that the degree of integration depends on the structure of wiring.
In addition, because of an increase in load on wirings, multi-layer wiring of three- to four-layer configuration is used at present. However, what comes into question because of the multi-layer wiring is techniques for interconnecting wirings.
In order to interconnect wirings, openings must be provided in insulating films for each layer, and hence it has been hitherto necessary in the case of, e.g., four-layer wiring, to carry out patterning end etching for providing openings simply at least four times.
FIGS. 6A and 6B are schematic representation of the structure of an MOS transistor to illustrate the wiring structure of conventional multi-layer wiring, in which FIG. 6A is a top view thereof and FIG. 6B a cross-sectional view taken along the line B-B' in FIG. 6A.
In FIGS. 6A and 6B, reference numeral 201 denotes a semiconductor substrate (with a conductivity type reverse to that of a first conductivity type); 202, a device separating region (LOCOS); 203, a gate oxide film; 204, a gate electrode; 205, a drain region (a first conductivity type region); 206, an insulating film; 205, a second conductivity type wiring; 208, an interlayer insulating film; 209, a third conductivity type wiring; 210, an opening made secondly; and 211, an opening made firstly.
In the device shown in FIGS. 6A and 6B, the opening 211 is made toward the drain region 205 (a first conductivity type region) for its connection to the second conductivity type wiring 205, and then the opening 210 is made so as to connect the wiring 205 to the third conductivity type wiring 209. In setting up such connection, the operations in twice to make openings enable conduction of the potential of the drain 205 to the upper layer wiring 209.
Here, the area of the opening can be made smaller and after all the degree of integration of a semiconductor device can be increased if the second-time opening 210 can be provided on the first-time opening 211.
For such purpose, research has been done to provide the second-time opening on the first-time opening. FIGS. 7A and 7B illustrate an example of the steps of overlapping such openings. In FIGS. 7A and 7B, reference numeral 401 denotes a semiconductor substrate; 402, a drain region serving also as a first conductivity type wiring; 403, an insulating film; 404, a second conductivity type wiring; 405, an interlayer insulating film; 406, a resist layer; 407, a resist residue; 408, an etching gas; and 409, a third conductivity type wiring. In this example, the second and the third conductivity type wirings 404 and 409 are connected to the drain region 402 at the same opening. In FIGS. 7A and 7B, FIG. 7A is a schematic cross-sectional view of the step of etching to make the second-time opening, and FIG. 7B is a schematic cross-sectional view when the third conductivity type wiring is provided after the etching. In these steps, the insulating film 403 is first etched to make an opening. Next, the second conductivity type wiring 404 is provided, then the interlayer insulating film 405 is provided thereon, and the resist layer 406 is further provided thereon. Now, the resist layer 406 is patterned and the interlayer insulating film 405 is selectively etched by the etching gas 408 (FIG. 7A). Then the third conductivity type wiring 409 is provided (FIG. 7B).
Here, as shown in FIGS. 7A and 7B, since the resist residue 407 remains in the opening, a part of an interlayer insulating film 405' remains unetched, even if the selective etching is carried out when the second-time opening is formed. Hence, the second conductivity type wiring and the third conductivity type wiring can not be well connected thereby causing problems of an increase in contact resistance and a lowering of reliability.
Since also the two layers of the insulating film 403 and the interlayer insulating film 405 are separately etched, the step of masking must be taken twice. Thus, there is another problem that the same cost as in the connection as shown in FIGS. 7A and 7B is required.